AN INTRODUCTION TO VME
VME bus (Versa Module Europa) is a flexible open-ended bus system which makes use of the Eurocard standard. It was introduced by Motorola, Phillips, Thompson, and Mostek in 1981. VME bus was intended to be a flexible environment supporting a variety of computing intensive tasks, and has become a very popular protocol in the computer industry. It is defined by the IEEE 1014-1987 standard.
The bus usage was developed from a computing point of view, which leads to a completely memory mapped scheme. Every device can be viewed as an address, or block of addresses. Under VME, addresses and data are not multiplexed. A block transfer, however, is possible for DMA style applications. The bus allows multiple masters, and contains a powerful interrupt scheme. A resource manager is required to handle the interrupts. The VME bus is a TTL based backplane which, although the system is asynchronous, sets the data transfer speed to approximately 20 Mbytes per second.
A typical transfer consists of an arbitration cycle (to gain bus control), an address cycle (to select the register) and the actual data cycle. Read, write, modify and block transfers are supported.
The VME bus system consists of 4 sub-buses: the Data Transfer Bus, the Arbitration Bus, the Priority Interrupt Bus and the Utility Bus. Data transfer is asynchronous supporting modules with a broad variety of response times.
CRATE AND MODULE MECHANICS
The system is modular and follows the Eurocard standard. VME card cages contain 21 slots, the first of which must be used as a crate manager. The usual card sizes are 160 x 216 mm and 160 x 100 mm. Cards of both sizes can be mixed in the same crate. The smaller cards are capable of 8 or 16 bit transfers. The larger cards can perform 8, 16 or 32 bit transfers and also can support a larger address range (4 Gbytes vs. 16 Mbytes). All VME boards have a P1 connector (see PIN ASSIGNMENTS). Larger cards may be equipped with the optional P2 connector. Crates may support both connectors or (in less expensive systems) only P1.
A module controlling the bus will drive the bus busy line (BBSY) low to show that it is in use. When this line is not low the arbiter module will sample the bus request lines (BR0-BR3) looking for a pending action. Requests on BR3 have the highest priority. Requests of equal priority are handled by a daisy chain using the bus grant in lines (BG0IN-BG3IN) and the bus grant out lines (BG0OUT-BG3OUT). The arbiter module which sits in slot 1 generates the first grant signal and this is passed to modules of increasing slot number.
DATA TRANSFER BUS
The data transfer bus is used for reading and writing data between modules. The data bus (D00-D31) holds the actual data during a transfer. The address of the register being accessed is presented on the address bus (A01-A31). The address modifier lines (AM00-AM05) indicate the length of the address, the kind of data cycle and the master identifier. The address strobe (AS) is used to signal the presence of a valid address. The data strobes (DS0,DS1) are used by the module controlling the transfer (master) to signal the presence and acceptance of valid data on the bus along with information on the size of the word to be transferred (together with the long word select, LWORD). The WRITE line is used to distinguish between read and write operations. The data transfer acknowledge (DTACK) is used by the module being accessed (slave) to signal the completion of a transfer. Errors in this transfer are signaled using the bus error line (BERR).
PRIORITY INTERRUPT BUS
Normally only one processor is dedicated to handling interrupts by monitoring the interrupt request lines (IRQ1-IRQ7). IRQ7 has the highest priority. In response to an interrupt, an address cycle is generated where the address indicates the request being acknowledged. The interrupt acknowledge (IACK) is changed in the arbiter to a signal which is daisy chained down the bus using the interrupt acknowledge in pin (IACKIN) and interrupt acknowledge out pin (IACKOUT). A data cycle follows where the module requesting the interrupt asserts its status and ID.
Power is supplied to modules via pins at +5 V, -12 V and +12 V. An optional battery backup of the +5 V supply (+5STDBY) can also be present. The utility bus supports an independent 16 MHz system clock (SYSCLK). The system failure line (SYSFAIL) and AC failure line (ACFAIL) are bussed lines used to indicate global problems. The system reset line (SYSRESET) is used for initialization. Additional data transfers can take place along the serial data line (SERDAT) and are synchronized with the serial clock line (SERCLK).
Complete documentation on the VME bus can be found in many references. In particular, Vita, the VME bus International Trade Association, has been found to be very helpful: Vita, Suite E, 10229 N. Scottsdale Road, Scottsdale, AZ 85253, Phone: (602) 951-8866.